    I1 (net30 net31 CinH CinL SumH SumL Vdd Vdd\- Vss Vss\+) SupplyBiasXor
    I0 (Ah Al Bh Bl net30 net31 Vdd Vdd\- Vss Vss\+) SupplyBiasXor
    I4 (net46 net47 net56 net57 COutH COutL Vdd Vdd\- Vss\+ Vss) NAND
    I3 (CinH CinL net30 net31 net46 net47 Vdd Vdd\- Vss\+ Vss) NAND
    I2 (Ah Al Bh Bl net56 net57 Vdd Vdd\- Vss\+ Vss) NAND
ends SupplyBiasFullAdder
// End of subcircuit definition.
